1. Field of the Invention
The present invention relates to a semiconductor device and more particularly to a semiconductor device in which an electrode is drawn out of the backside of an on-board semiconductor chip.
2. Description of the Related Art
As a form of package used for semiconductor integrated circuits there is a PGA (pin grid array). The PGA is arranged such that external terminals or pins are fixed to a package body at regular intervals vertically and in the form of grid. The PGA is often used as a multi-terminal package.
Semiconductor devices used in high frequency bands each have an electrode formed on the entire backside of their respective semiconductor chip in order to stabilize their operating characteristics. Hereinafter, such an electrode is referred to as a backside electrode.
FIG. 6 shows a conventional semiconductor device having a PGA structure. In FIG. 6, the semiconductor device comprises a semiconductor chip 101, a chip-mounting section 102, a conducting path forming section 110, a plurality of bonding wires 103, a heat sinking board 104, and a plurality of pin-like external terminals 112. The semiconductor chip 101 has an electrode formed on its backside. The semiconductor chip 101 is mounted on the chip-mounting section 102. The conducting path forming section is disposed around the edges of the chip-mounting section 102 and have a plurality of conducting paths 111 formed inside. The bonding wires 103 connect pad electrodes (not shown) formed on the semiconductor chip 101 and the chip-mounting section 102 to corresponding respective ones of the conduction paths 111. The heat sink 104 is bonded to the backside of each of the chip-mounting section 102 and the conductive-path forming section 110. The chip-mounting section 102 is made of an insulating material and coated on top with a conductive film not shown. The external terminals 112 are provided on the top of the conducting path forming section 110 and electrically connected to the respective ones of the conduction paths 111.
FIG. 7 is an enlarged view of the semiconductor chip 101, the chip-mounting section 102, and the conduction path forming section 110. In this FIGURE, the conduction paths 111 are provided radially on first and second insulating layers 113 and 114. Each of pad electrodes 115 on the semiconductor chip 101 is connected to a respective one of the conduction paths 111 by a bonding wire 103. The backside electrode of the semiconductor chip 101 is electrically connected to the conductive film 102a on the top of the chip-mounting section 102, which, in turn, is connected to a conduction path 111a on the first insulating layer 113 by bonding wires 103.
It is thus required that the conductive film 102a on the chip-mounting section 102 be wire-bonded to the conduction path 111a when the semiconductor chip 101 is coated underneath with an electrode. In this case, as shown in FIG. 7, this wire bonding is performed at corners of the chip-mounting section 102 and the conduction path forming section 110, which offers little obstruction to wire bonding of the pad electrodes on the chip and allows the bonding area to be increased.
The reliability of semiconductor devices is significantly affected by wire bonding. Thus, good bonding must be effected at all connection points. In general, however, there is a tendency that, when a wire used is short, the resulting wire loop becomes low in height and, when a wire used is too long, it comes loose to form an underloop. In other words, the bonding wires must lie within an appropriate range of length. When a wire is short, it is liable to peel off the point where it has been bonded. When a wire is too long, on the other hand, it may come in contact with another portion. For this reason, the length of the bonding wires between the conductive film 102a on the chip-mounting section 102 and the conduction path 111a must be set appropriately.
The wire bonding is performed by the use of a capillary and hence there is a need for a space where it can move. In wire bonding for the semiconductor chip 101 and the conduction path 111a in particular, the space where the capillary moves must be fully taken into consideration because the semiconductor chip 101 or the second insulating layer 114 of the conduction path forming section 110 forms a difference in level within the space for movement of the capillary. That is, assuming the shortest distance between a point of bonding on the conductive film 102a and the corner of the semiconductor chip to be L1 and the shortest distance between a point of bonding on the conduction path 111a and the corner of the second insulating layer 114 to be L2, these distances L1 and L2 must be set to the shortest distance required for bonding over which the capillary can move. Thus, the size W of the cavity shown in FIG. 6, or the inside diameter of the conductive path forming section 110, is defined by the size of the semiconductor chip 101 and the space needed for wire bonding at the corners.
FIG. 8 shows cavity size versus semiconductor chip size. When no wire bonding is performed on the chip-mounting section 102 and the conduction path forming section 110, the semiconductor chip size is allowed to lie in the range defined by lines A1 and A2. When wire bonding is performed, on the other hand, the chip size must lie within the range defined by lines A1 and A3. To be specific, assume that the cavity size is 10 mm. If, in this case, no wire bonding is performed, the semiconductor chip size can range from 4.0 to 7.0 mm. When wire bonding is performed, the chip size must range from 4.0 to 5.0 mm. That is, when the chip-mounting section 102 and the conduction path forming section 110 need to be connected with each other by wire bonding, the chip size is restricted within narrow limits, decreasing the versatility of the conduction path forming section (cavity) 110 or the semiconductor chip 101.
As described above, since the chip-mounting section 102 and the conduction path forming section 110 are wire bonded so as to connect the backside electrode of the semiconductor chip and the conduction path forming section 110 with each other, a space must be reserved for wire bonding. This restricts the size of a semiconductor chip.